1. Field of the Invention
The present invention relates to a chip battery including a solid electrolyte.
2. Description of the Related Art
A chip battery includes an element body including, for example, a solid electrolyte layer and positive and negative electrode layers provided on both surfaces of the solid electrolyte layer. In addition, terminal electrodes are provided on the positive and negative electrode layers of the element body. In order to increase the battery capacity of such a chip battery, it is necessary to increase the amount of the electrode active material included in each of the positive and negative electrode layers. Also, in order to increase the output current, it is necessary to increase the opposing area between the terminal electrode and the positive electrode layer and the opposing area between the terminal electrode and the negative electrode layer. On the other hand, chip batteries are often mounted on substrates, and chip batteries are required to have a lower profile as other devices have lower profiles.
In order to satisfy these conditions, a solid electrolyte layer, a positive electrode layer, a negative electrode layer, and terminal electrodes are preferably laminated in a direction substantially perpendicular to a mounting surface of a chip battery. However, when terminal electrodes are provided on both sides in the direction substantially perpendicular to a mounting surface of a chip battery, it is necessary to perform wire bonding between the terminal electrode on the upper surface and a substrate and to accommodate the chip battery in a package which can be surface-mounted, thereby preventing surface-mounting of the chip battery as a single unit. In order to surface-mount a chip battery, terminal electrodes are preferably provided on both ends in a direction substantially perpendicular to the lamination direction of an element body as in a chip capacitor.
Therefore, a configuration of a chip battery is shown in FIGS. 8A and 8B. A chip battery 1 includes a solid electrolyte layer 2. In addition, a positive electrode layer 3 is provided on one of the surfaces of the solid electrolyte layer 2, and a negative electrode layer 4 is provided on the other surface of the solid electrolyte layer 2. Further, current collectors 5a and 5b are provided on the positive electrode layer 3 and the negative electrode layer 4, respectively. The positive electrode layer 3 and the current collector 5a are arranged so as to extend from one of the ends to the other end in a direction substantially perpendicular to the lamination direction of the solid electrolyte layer 2 and the positive and negative electrode layers 3 and 4 and so as not to be exposed at the other end. The negative electrode layer 4 and the current collector 5b are arranged so as to extend from the other end to the one end in a direction substantially perpendicular to the lamination direction of the solid electrolyte layer 2 and the positive and negative electrode layers 3 and 4 and so as not to be exposed at the one end.
Furthermore, an insulator layer 6 is provided on each of the current collectors 5a and 5b. In addition, terminal electrodes 7 and 8 are provided on both end surfaces of the laminate in a direction substantially perpendicular to the lamination direction thereof. The ends of the positive electrode layer 3 and the current collector 5a are electrically connected to one 7 of the terminal electrodes. The ends of the negative electrode layer 4 and the current collector 5b are electrically connected to the other terminal electrode 8. Further, a resin layer 9 is provided on each of the lamination surfaces of the laminate between the terminal electrodes 7 and 8.
In such a chip battery 1, good charge-discharge properties can be achieved by optimizing the thickness of each of the solid electrolyte layer 2 and the positive and negative electrode layers 3 and 4. Also, the current collectors 5a and 5b are brought into line contact with the terminal electrodes 7 and 8, respectively, thereby decreasing the area of the contact portions between the current collectors 5a and 5b and the terminal electrodes 7 and 8. Therefore, even when unit cells are laminated to define a chip battery having a multi-cell structure, a small chip battery without increasing the mounting area can be achieved (refer to Japanese Unexamined Patent Application Publication No. 2002-352850).
The chip battery shown in FIG. 8 includes the element body including layers laminated in a direction substantially perpendicular to a mounting surface, and the terminal electrodes provided on both end surfaces of the element body in a direction substantially perpendicular to the lamination direction thereof, thereby permitting surface mounting. However, since a current collector is brought into line contact with each terminal electrode, the contact area therebetween and the reliability of connection between the current collector and the terminal electrode are decreased and the internal resistance of the chip battery is increased.